Pre-start listener routine, rev4. To insert: Change the LCALL to 68A1 (-607) or 6827 (-608) in the prestart loop at 0x3C69 (-607) or 0x3BEF (-608) to LCALL 0x8800. Place the following bytes at 0x8800, which are the original bytes from the 68A1/6827 routine. Same bytes in both 607 and 608: D2 2A 75 DC 04 75 DA 00 20 DC FD E5 D9 85 DA F0 30 2A ED F5 7C 85 F0 7D 00 Then follow with the bytes of this routine. ------------------ 90 FD AE E0 F5 F0 30 F3 01 22 90 FD C4 E0 F9 90 FD C5 E0 FA 74 01 C3 29 B4 41 14 E4 F9 90 FD C4 F0 74 01 2A B4 05 01 E4 90 FD C5 F0 FA 80 05 F9 90 FD C4 F0 E9 B4 01 37 E5 F0 53 E0 C0 B4 00 02 C2 34 B4 40 02 D2 34 B4 80 0D EA B4 00 02 D2 34 B4 02 02 C2 34 80 18 B4 C0 15 EA B4 00 02 C2 34 B4 01 02 D2 34 B4 02 02 C2 34 B4 03 02 D2 34 30 F5 65 90 FD AF E0 FC 90 FD B0 E0 FD 74 01 2C FC 50 1B 74 01 2D FD 50 15 C2 F5 E5 F0 90 FD AE F0 E4 90 FD AF F0 90 FD B0 F0 75 98 50 22 90 FD AF EC F0 90 FD B0 ED F0 8C 82 8D 83 75 AA FC 75 BA 03 43 98 40 53 98 6F C2 AC E5 83 F5 99 30 99 FD C2 99 E5 82 F5 99 30 99 FD C2 99 E0 F5 99 30 99 FD C2 99 75 98 40 22 30 F1 06 E4 90 FD AE F0 22 75 AA FC 75 BA 03 43 98 50 53 98 7F 43 87 80 43 D8 80 C2 AC D2 2A 75 DC 00 75 DA 00 20 DC FD E5 D9 30 2A F0 B4 80 00 40 1B 90 FD B0 E0 B4 08 00 50 0A 04 F0 7D 64 C2 9C 12 86 0D 22 90 FD C6 E0 D2 E2 F0 22 90 FD C6 E0 30 E2 2C 90 FD B1 E0 B4 08 00 50 0A 04 F0 7D 75 C2 9C 12 86 0D 22 90 FD B0 E4 F0 A3 F0 90 FD C6 F0 E5 F0 24 40 F5 F0 90 FD AE F0 12 87 17 22 E5 98 20 E0 04 75 98 50 22 E5 99 FB 53 98 EE 75 99 52 30 99 FD C2 99 BB 31 12 D2 F6 C2 F7 E5 F0 90 FD AE F0 75 99 21 30 99 FD C2 99 BB 32 12 C2 F6 D2 F7 E5 F0 90 FD AE F0 75 99 40 30 99 FD C2 99 BB 33 12 D2 F6 D2 F7 E5 F0 90 FD AE F0 75 99 23 30 99 FD C2 99 BB 6C 12 D2 F0 C2 F2 E5 F0 90 FD AE F0 75 99 6C 30 99 FD C2 99 BB 64 12 C2 F0 C2 F2 E5 F0 90 FD AE F0 75 99 64 30 99 FD C2 99 BB 78 21 75 F0 20 E5 F0 90 FD AE F0 90 FD AF 74 FF F0 90 FD B0 74 F7 F0 75 99 58 30 99 FD C2 99 75 98 40 22 BB 73 17 D2 F2 C2 F0 E5 F0 90 FD AE F0 90 FD B0 E4 F0 75 99 53 30 99 FD C2 99 BB 70 3F E5 80 F5 99 30 99 FD C2 99 E5 90 F5 99 30 99 FD C2 99 E5 A0 F5 99 30 99 FD C2 99 E5 B0 F5 99 30 99 FD C2 99 E5 E8 F5 99 30 99 FD C2 99 E5 F8 F5 99 30 99 FD C2 99 E5 FA F5 99 30 99 FD C2 99 BB 6F 1E 75 F0 08 E5 F0 90 FD AE F0 75 99 4F 30 99 FD C2 99 75 98 90 75 BA 03 75 AA CC 53 87 7F 22 12 87 17 75 98 50 22 ------------------ Values: B Per-loop holding for flagbyte - B register because it's bit addressable, unlike R(x). R1 Counter low byte storage R2 Counter high byte storage R3 Per-loop holding for S0BUF receive byte R4 XRAM dump address counter, low byte R5 XRAM dump address counter, high byte 0xFDAE Flagbyte 0xFDC4 Cycle counter, low byte (counter for timing MIL flashing) 0xFDC5 Cycle counter, high byte (counter for timing MIL flashing) 0xFDC6 Additional flagbyte, used for TPS mapswitch stuff XRAM 0xFDAE logflag bits: 0: Request Logging 1: Request ACK from drive cycle logging routine 2: XRAM streaming mode 3: Request for pre-start OBD-II -- Abandon listener routine until next drivecycle (drivecycle routine clears bit) 4: unused 5: XRAM dump in progress 6: Map Switch bit 1 7: Map Switch bit 2 ----- CODE START ; Get Flagbyte to B register 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte E0 MOVX A, @DPTR ; Get byte to ACC F5 F0 MOV B, A ; Move to B ; Handle pre-start OBD-II request - Abandon ship if this is set. 30 F3 01 JNB B.3 +1 ; Pre-start OBD-II not requested, skip over return 22 RET ; Get Counter Low/High from XRAM to R1/R2 90 FD C4 MOV DPTR, #0xFDC4 ; CounterLow E0 MOV A, @DPTR F9 MOV R1, A ; in R1 90 FD C5 MOV DPTR, #0xFDC5 ; CounterHigh E0 MOV A, @DPTR FA MOV R2, A ; in R2 ; Increment R1 and R2, checking for carry to spin high at 64 74 01 MOV A, #1 ; For addition C3 CLR C ; Ensure carry is clear 29 ADD A, R1 ; Add CLOW to A -- CLOW +1 ; If we're at 64, reset to zero, INC the high byte B4 41 14 CJNE A, #0x41 +20 ; Loop at 64 E4 CLR A ; Reset to 0 F9 MOV R1, A ; Update CLOW in R1 90 FD C4 MOV DPTR, #0xFDC4 ; CounterLow XRAM F0 MOV @DPTR, A ; Update CounterLow XRAM ; Do high byte 74 01 MOV A, #1 ; For addition 2A ADD A, R2 ; Add CHIGH to A -- CHIGH +1 B4 05 01 CJNE A, #0x05 ; Loop high byte at 5 E4 CLR A ; If we incremented to 5, clear (0) it. 90 FD C5 MOV DPTR, #0xFDC5 ; CounterHigh F0 MOV @DPTR, A ; Update CounterHigh XRAM FA MOV R2, A ; Update CHIGH in R2 80 05 SJMP +5 ; If we hit 64 and did this stuff, counter low was already updated, skip that ; Update counter low F9 MOV R1, A ; Update CLOW in R1 90 FD C4 MOV DPTR, #0xFDC4 ; CounterLow XRAM F0 MOV @DPTR, A ; Update CounterLow XRAM ; Do MIL flashy stuff.. But only when low byte is 01 E9 MOV A, R1 ; Loop counter low byte to A B4 01 37 CJNE A, #0x01 +55 ; Jump over if counter is not 0x01 E5 F0 MOV A, B ; Get flagbyte from B, to A 53 E0 C0 ANL A, 0xC0 ; Zero lower 6 bits of B -- 0x40 = Map 1 // 0x80 = Map 2 // 0xC0 = Map 3 ; Case when using stock maps B4 00 02 CJNE A, #0x00 +2 ; Skip next if mapbits != 0x00 C2 34 CLR RAM_26.4 ; Make sure MIL is on for stock mapset, as it usually is before the car is started ; Case when using alt map set 1 B4 40 02 CJNE A, #0x40 +2 ; Skip next if mapbits != 0x40 D2 34 SETB RAM_26.4 ; Make sure MIL is off to indicate first alt map set ; Case when using alt map set 2, turn MIL on and off at 128 increments of counter high byte B4 80 0D CJNE A, #0x80 +13 ; Skip next if mapbits != 0x80 EA MOV A, R2 ; Loop counter high byte to A B4 00 02 CJNE A, #0x00 +2 ; Jump over if counter is not 0x00 D2 34 SETB RAM_26.4 ; Make sure MIL is off B4 02 02 CJNE A, #0x02 +2 ; Jump over if counter is not 0x02 C2 34 CLR RAM_26.4 ; Make sure MIL is on 80 18 SJMP +24 ; ACC was replaced with counter, we're done with the MIL anyways, jump over the last conditional ; 31 ; Case when using alt map set 3, flash MIL 3 times B4 C0 15 CJNE A, #0xC0 +21 ; Skip next if mapbits != 0xC0 EA MOV A, R2 ; Loop counter high byte to A B4 00 02 CJNE A, #0x01 +2 ; Jump over if counter is not 0x00 C2 34 CLR RAM_26.4 ; Make sure MIL is on B4 01 02 CJNE A, #0x20 +2 ; Jump over if counter is not 0x01 D2 34 SETB RAM_26.4 ; Make sure MIL is off B4 02 02 CJNE A, #0x40 +2 ; Jump over if counter is not 0x02 C2 34 CLR RAM_26.4 ; Make sure MIL is on B4 03 02 CJNE A, #0x60 +2 ; Jump over if counter is not 0x03 D2 34 SETB RAM_26.4 ; Make sure MIL is off ;55 ; B.5 indicates we're doing an SRAM dump -- Get the byte, dump it, and bail.. keep looping until all is dumped, then clear B.5 30 F5 65 JNB B.5 +101 ; Get DPL/DPH from XRAM to R4/R5 90 FD AF MOV DPTR, #0xFDAF ; DPL E0 MOV A, @DPTR FC MOV R4, A 90 FD B0 MOV DPTR, #0xFDB0 ; DPH E0 MOV A, @DPTR FD MOV R5, A ; Increment R4 and R5, checking for carry 74 01 MOV A, #1 ; For addition 2C ADD A, R4 ; Add DPL to A -- DPL +1 FC MOV R4, A ; Update DPL 50 1B JNC +27 ; If DPL didn't roll, we can just jump to sending the byte 74 01 MOV A, #1 ; For addition 2D ADD A, R5 ; Add DPH to A -- DPH +1 FD MOV R5, A ; Update DPH 50 15 JNC +21 ; If DPH didn't roll either, we can just send the byte ; DPL/DPH rolled, we hit FFFF, bail C2 F5 CLR B.5 ; DPH rolled, we are done, clear the XRAM dumping bit E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Clear bytes used for DPTR E4 CLR A ; A = 0 90 FD AF MOV DPTR, #0xFDAF ; DPL XRAM F0 MOVX @DPTR, A ; Clear FDAF 90 FD B0 MOV DPTR, #0xFDB0 ; DPH XRAM F0 MOVX @DPTR, A ; Clear FDB0 ; Set serial port REN0 and exit 75 98 50 MOV S0CON, #0x50 ; Serial Mode1, REN0 Enabled 22 RET ; Just bail ; Update memory with the new DPTR first 90 FD AF MOV DPTR, #0xFDAF ; DPL XRAM EC MOV A, R4 F0 MOVX @DPTR, A ; Update XRAM 90 FD B0 MOV DPTR, #0xFDB0 ; DPH XRAM ED MOV A, R5 F0 MOVX @DPTR, A ; Update XRAM 8C 82 MOV DPL, R4 ; Update DPTR 8D 83 MOV DPH, R5 ; Update DPTR ; Init Serial Port 75 AA FC MOV S0RELL, 0xFC ; vvv 75 BA 03 MOV S0RELH, 0x3 ; S0REL = 0x3FC -- 125000 baud with SMOD set 43 98 40 ORL S0CON, 0x40 ; Set bit SM1 53 98 6F ANL S0CON, 0x6F ; Clear bit SM0 - Ensure Mode 1 8Bit UART, Disable REN C2 AC CLR IEN0.4 ; Turn off serial interrupt ; Dump byte, DPTR value first E5 83 MOV A, DPH ; Get the byte to send F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 82 MOV A, DPL ; Get the byte to send F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E0 MOV A, @DPTR ; Get the byte to send F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI 75 98 40 MOV S0CON, #0x40 ; Serial Mode1, REN0 Disabled (we'll turn it back on when we're done dumping) 22 RET ; Just bail ; END of XRAM dumper ; The running routine sets B.1 when it logs so we can distinguish drive cycles. ; If this is the first loop of pre-start after a drive cycle, clear all B bits. ; This allows us to distinguish drive cycles... Well, that is, if all this didn't get cleared each drivecycle anyways ; More useful when XRAM holding between drive cycles is figured out. 30 F1 06 JNB B.1, +6 ; B.1 is not set, jump over this routine E4 CLR A ; A = 0 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Clear flagbyte 22 RET ; Return. Resume processing on next loop. ; Init Serial Port 75 AA FC MOV S0RELL, 0xFC ; vvv 75 BA 03 MOV S0RELH, 0x3 ; S0REL = 0x3FC -- 125000 baud with SMOD set 43 98 50 ORL S0CON, 0x50 ; Set bits SM1 and REN0 53 98 7F ANL S0CON, 0x7F ; Clear bit SM0 - Ensure Mode 1 8Bit UART 43 87 80 ORL PCON, #0x80 ; set PCON0.7 (SMOD), bitrate doubler 43 D8 80 ORL ADCON0, #0x80 ; Set ADCON0.7 (BD), enable baud rate generator C2 AC CLR IEN0.4 ; Turn off serial interrupt ; ADC THE TPS, jump over throttle depressed block if it's not depressed. D2 2A SETB RAM_25.2 75 DC 00 MOV ADCON1, #0 ; ADC channel 0: TPS 75 DA 00 MOV DAPR, #0 ; Initiate conversion 20 DC FD JB ADCON0.4, $ ; Wait for conversion E5 D9 MOV A, ADDAT ; Move result to ACC 30 2A F0 JNB RAM_25.2 -13 B4 80 00 CJNE A, 0x80, NEXT ; Compare to 0x80 (2.50v) 40 1B JC +27 ; Jump if throttle is not depressed (ADDAT returned < 0x80) ; throttle depressed. Check for 8 ADCs > 0x80 using FBD0 counter. If throttle is depressed, but <8 ADCs, spin counter and loop 90 FD B0 MOV DPTR, #0xFDB0 ; TPS ADC counter E0 MOVX A, @DPTR ; Fetch to ACC B4 08 00 CJNE A, 8 ; Compare ACC (FDB0) to 8, set carry if <8 50 0A JNC +10 ; Carry not set, counter >8, don't INC counter and return 04 INC A ; Increment counter F0 MOVX @DPTR, A ; Update FDB0 Counter 7D 64 MOV R5, 44 ; "d" C2 9C CLR S0CON.4 ; Clear REN0 for send 12 86 0D LCALL CODE_860D ; Send d to indcate throttle is down, but not 8 counts 22 RET ; Loop ; throttle is down, and we have >8 catches. Update TPS flagbyte to indicate. 90 FD C6 MOV DPTR, #0xFDC6 ; TPS flagbyte E0 MOV A, @DPTR D2 E2 SETB ACC.2 ; Set bit 2 of flagbyte to indicate we have >8 cycles of throttle down F0 MOV @DPTR, A ; Update flagbyte 22 RET ; throttle is still down. Loop, waiting for it to be released ; Jump to here when the throttle is up. Check if it's been up for 8 cycles... But only is throttle depression set FDC6.2, meaning we've changed state. 90 FD C6 MOV DPTR, #0xFDC6 ; TPS flagbyte E0 MOV A, @DPTR 30 E2 2C JNB ACC.2 +44 ; Jump over this if throttle wasn't previously depressed for >8 cycles. 90 FD B1 MOV DPTR, #0xFDB1 ; TPS ADC counter (up state) E0 MOVX A, @DPTR ; Fetch to ACC B4 08 00 CJNE A, 8 ; Compare ACC (FDB0) to 8, set carry if <8 50 0A JNC +10 ; Carry not set, counter >8, don't INC counter and return 04 INC A ; Increment counter F0 MOVX @DPTR, A ; Update FDB0 Counter 7D 75 MOV R5, 75 ; "u" C2 9C CLR S0CON.4 ; Clear REN0 for send 12 86 0D LCALL CODE_860D ; Send u to indcate throttle is down, but not 8 counts 22 RET ; Loop, increment counter again next cycle if throttle still up ; throttle is up, and we have >8 catches, after we caught 8 downs. Clear stuff out and select the next map set. 90 FD B0 MOV DPTR, #0xFDB0 ; FDB0 TPS ADC Counter (depressed) E4 CLR A ; Clear A F0 MOVX @DPTR, A ; Clear FDB0 A3 INC DPTR ; INC DPTR - FDB1 TPS ADC Counter (up) F0 MOVX @DPTR, A ; Clear FDB1 90 FD C6 MOV DPTR, #0xFDC6 ; TPS Byte F0 MOVX @DPTR, A ; TPS Byte ; Then increment the map bits E5 F0 MOV A, B ; Get flagbyte from B 24 40 ADD A, #0x40 ; Add 0x40 to A which increments bytes 6/7 F5 F0 MOV B, A ; Move back to B 90 FD AE MOV DPTR, #0xFDAE ; XRAM for flagbyte F0 MOVX @DPTR, A ; update XRAM 12 87 17 LCALL CODE_8717 ; Send flagbyte in ASCII 22 RET ; Check for pending serial input E5 98 MOV A, S0CON 20 E0 04 JB ACC.0, +4 ; Got input, step over return ; No input, set Mode1 + REN0 and return 75 98 50 MOV S0CON, #0x50 ; Bits SM1 and REN0 22 RET ; Get S0BUF and send "R" to ack input E5 99 MOV A, S0BUF ; MOV received byte to ACC FB MOV R3, A ; Store received byte in R3 53 98 EE ANL S0CON, #0xEE ; Clear RI0 and REN0 75 99 52 MOV S0BUF, #0x52 ; Send R 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "1": Map switch, set 1 BB 31 12 CJNE R3, #0x31, +18 ; Compare to "1" D2 F6 SETB B.6 ; Set mapbit 1 C2 F7 CLR B.7 ; Clear mapbit 2 E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send ! to ack 75 99 21 MOV S0BUF, #0x21 ; Send "!" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "2": Map switch, set 2 BB 32 12 CJNE R3, #0x32, +18 ; Compare to "2" C2 F6 CLR B.6 ; Clear mapbit 1 D2 F7 SETB B.7 ; Set mapbit 2 E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send @ to ack 75 99 40 MOV S0BUF, #0x40 ; Send "@" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "3": Map switch, set 3 BB 33 12 CJNE R3, #0x33, +18 ; Compare to "3" D2 F6 SETB B.6 ; Set mapbit 1 D2 F7 SETB B.7 ; Set mapbit 2 E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send # to ack 75 99 23 MOV S0BUF, #0x23 ; Send "#" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "l" to enable logging BB 6C 12 CJNE R3, #0x6C, +18 ; Compare to "l" D2 F0 SETB B.0 ; Set bit 1, log enable C2 F2 CLR B.2 ; Disable streaming logging, in case that was previously set E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send l to ack 75 99 6C MOV S0BUF, #0x6C ; Send "l" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "d" to disable logging BB 64 12 CJNE R3, #0x64, +18 ; Compare to "d" C2 F0 CLR B.0 ; Clear logging flagbit C2 F2 CLR B.2 ; Disable streaming logging, in case that was previously set E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send d to ack 75 99 64 MOV S0BUF, #0x64 ; Send "d" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for "x", do XRAM dump BB 78 21 CJNE R3, #0x78, +33 ; Compare to "x" 75 F0 20 MOV B, #20 ; Set bit 5 only E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte 90 FD AF MOV DPTR, #0xFDAF ; Update DPL in XRAM 74 FF MOV A, #FF F0 MOVX @DPTR, A 90 FD B0 MOV DPTR, #0xFDB0 ; Update DPH in XRAM 74 F7 MOV A, #F7 F0 MOVX @DPTR, A ; Send X to ack and bail with REN0 off - Next time into this loop, we'll start dumping 75 99 58 MOV S0BUF, #0x78 ; Send "x" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI 75 98 40 MOV S0CON, #0x40 ; Serial Mode1, REN0 Disabled (we'll turn it back on when we're done dumping) 22 RET ; Just bail, XRAM dump will start next loop ; Check for incoming "s", XRAM streaming mode BB 73 17 CJNE R3, #0x73, +23 ; Compare to "s" D2 F2 SETB B.2 ; Set bit 1, log enable C2 F0 CLR B.0 ; Disable normal logging, in case that was previously set E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte 90 FD B0 MOV DPTR, #0xFDB0 ; DPTR to FDB0, cycle counter for XRAM dumper E4 CLR A ; ACC = 0 F0 MOVX @DPTR, A ; Set counter byte to 0 ; Send R to ack 75 99 53 MOV S0BUF, #0x53 ; Send "S" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "p" to dump port SFRs BB 70 3F CJNE R3, #0x70, +63 ; Compare to "p" E5 80 MOV A, P0 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 90 MOV A, P1 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 A0 MOV A, P2 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 B0 MOV A, P3 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 E8 MOV A, P4 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 F8 MOV A, P5 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 FA MOV A, P6 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "o" to enable pre-start OBD-II BB 6F 1E CJNE R3, #0x6F, +30 ; Compare to "o" 75 F0 08 MOV B, #8 ; bit 3, prestart OBDII - everything else cleared. E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send "O" 75 99 4F MOV S0BUF, #0x4F ; Send O 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Reapply the settings found in the RESET routine used to initally configure the serial port 75 98 90 MOV S0CON, #0x90 75 BA 03 MOV S0RELH, #3 75 AA CC MOV S0RELL, #0xCC 53 87 7F ANL PCON, #7F 22 RET ; Send current logbyte, bit by bit in ASCII for readablity. 12 87 17 LCALL CODE_8717 ; Now in external function ; End of subroutine 75 98 50 MOV S0CON, #0x50 ; Serial Mode1, REN0 Enabled 22 RET