Listener routine, rev2. To insert: Change the LCALL to 68A1 (-607) or 6827 (-608) in the prestart loop at 0x3C69 (-607) or 0x3BEF (-608) to LCALL 0x8800. Place the following bytes at 0x8800, which are the original bytes from the 68A1/6827 routine. Same bytes in both 607 and 608: D2 2A 75 DC 04 75 DA 00 20 DC FD E5 D9 85 DA F0 30 2A ED F5 7C 85 F0 7D 00 Then follow with the bytes of this routine. ------------------ Values: B Per-loop holding for flagbyte - B register because it's bit addressable, unlike R(x). R3 Per-loop holding for S0BUF receive byte 0xFDAE Flagbyte Memory Address XRAM 0xFDAE logflag bits: 0: Request Logging 1: Request ACK from drive cycle logging routine 2: XRAM streaming mode 3: Request for pre-start OBD-II -- Abandon listener routine until next drivecycle (drivecycle routine clears bit) 4: unused 5: XRAM dump in progress 6: Map Switch bit 1 7: Map Switch bit 2 ----- ; Get Flagbyte to B register 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte E0 MOVX A, @DPTR ; Get byte to ACC F5 F0 MOV B, A ; Move to B ; Handle pre-start OBD-II request - Abandon ship if this is set. 30 F3 01 JNB B.3 +1 ; Pre-start OBD-II not requested, skip over return 22 RET ; B.5 indicates we're doing an SRAM dump -- Get the byte, dump it, and bail.. keep looping until all is dumped, then clear B.5 30 F5 65 JNB B.5 +101 ; Get DPL/DPH from XRAM to R4/R5 90 FD AF MOV DPTR, #0xFDAF ; DPL E0 MOV A, @DPTR FC MOV R4, A 90 FD B0 MOV DPTR, #0xFDB0 ; DPH E0 MOV A, @DPTR FD MOV R5, A ; Increment R4 and R5, checking for carry 74 01 MOV A, #1 ; For addition 2C ADD A, R4 ; Add DPL to A -- DPL +1 FC MOV R4, A ; Update DPL 50 1B JNC +27 ; If DPL didn't roll, we can just jump to sending the byte 74 01 MOV A, #1 ; For addition 2D ADD A, R5 ; Add DPH to A -- DPH +1 FD MOV R5, A ; Update DPH 50 15 JNC +21 ; If DPH didn't roll either, we can just send the byte ; DPL/DPH rolled, we hit FFFF, bail C2 F5 CLR B.5 ; DPH rolled, we are done, clear the XRAM dumping bit E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Clear bytes used for DPTR E4 CLR A ; A = 0 90 FD AF MOV DPTR, #0xFDAF ; DPL XRAM F0 MOVX @DPTR, A ; Clear FDAF 90 FD B0 MOV DPTR, #0xFDB0 ; DPH XRAM F0 MOVX @DPTR, A ; Clear FDB0 ; Set serial port REN0 and exit 75 98 50 MOV S0CON, #0x50 ; Serial Mode1, REN0 Enabled 22 RET ; Just bail ; Update memory with the new DPTR first 90 FD AF MOV DPTR, #0xFDAF ; DPL XRAM EC MOV A, R4 F0 MOVX @DPTR, A ; Update XRAM 90 FD B0 MOV DPTR, #0xFDB0 ; DPH XRAM ED MOV A, R5 F0 MOVX @DPTR, A ; Update XRAM 8C 82 MOV DPL, R4 ; Update DPTR 8D 83 MOV DPH, R5 ; Update DPTR ; Init Serial Port 75 AA FC MOV S0RELL, 0xFC ; vvv 75 BA 03 MOV S0RELH, 0x3 ; S0REL = 0x3FC -- 125000 baud with SMOD set 43 98 40 ORL S0CON, 0x40 ; Set bit SM1 53 98 6F ANL S0CON, 0x6F ; Clear bit SM0 - Ensure Mode 1 8Bit UART, Disable REN C2 AC CLR IEN0.4 ; Turn off serial interrupt ; Dump byte, DPTR value first E5 83 MOV A, DPH ; Get the byte to send F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 82 MOV A, DPL ; Get the byte to send F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E0 MOV A, @DPTR ; Get the byte to send F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI 75 98 40 MOV S0CON, #0x40 ; Serial Mode1, REN0 Disabled (we'll turn it back on when we're done dumping) 22 RET ; Just bail ; END of XRAM dumper ; The running routine sets B.1 when it logs so we can distinguish drive cycles. ; If this is the first loop of pre-start after a drive cycle, clear all B bits. ; This allows us to distinguish drive cycles. 30 F1 06 JNB B.1, +6 ; B.1 is not set, jump over this routine E4 CLR A ; A = 0 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Clear flagbyte 22 RET ; Return. Resume processing on next loop. ; Init Serial Port 75 AA FC MOV S0RELL, 0xFC ; vvv 75 BA 03 MOV S0RELH, 0x3 ; S0REL = 0x3FC -- 125000 baud with SMOD set 43 98 50 ORL S0CON, 0x50 ; Set bits SM1 and REN0 53 98 7F ANL S0CON, 0x7F ; Clear bit SM0 - Ensure Mode 1 8Bit UART 43 87 80 ORL PCON, #0x80 ; set PCON0.7 (SMOD), bitrate doubler 43 D8 80 ORL ADCON0, #0x80 ; Set ADCON0.7 (BD), enable baud rate generator C2 AC CLR IEN0.4 ; Turn off serial interrupt ; Check for throttle input >0x80 to activate map set 1 75 DC 00 MOV ADCON1, #0 ; ADC channel 0: TPS 75 DA 00 MOV DAPR, #0 ; Initiate conversion 20 DC FD JB ADCON0.4, $ ; Wait for conversion E5 D9 MOV A, ADDAT ; Move result to ACC B4 80 00 CJNE A, 0x80, NEXT ; Compare to 0x80 (2.50v) 40 21 JC +33 ; Jump over map setting if A is smaller than 0x80 (IE: throttle is not at position >0x80 ADC) ; Check for 5 ADCs > 0x80 using FBD0 counter 90 FD B0 MOV DPTR, #0xFDB0 ; TPS ADC counter E0 MOVX A, @DPTR ; Fetch to ACC B4 05 00 CJNE A, 5 ; Compare ACC (FDB0) to 5, set carry if <5 50 03 JNC +3 ; Carry not set, TPS ADC >=5, jump to it 04 INC A ; Increment counter F0 MOVX @DPTR, A ; Update FDB0 Counter 22 RET ; Loop ; Clear counter, then set map E4 CLR A ; Clear A F0 MOVX @DPTR, A ; Clear FDB0 Counter D2 F6 SETB B.6 ; Set mapbit 1 C2 F7 CLR B.7 ; Clear mapbit 2 E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send ! to ack 75 99 21 MOV S0BUF, #0x21 ; Send "!" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Return 22 RET ; Since we didn't ADC the TPS > 0x80, clear the TPS ADC counter. 90 FD B0 MOV DPTR, #0xFDB0 ; TPS ADC counter E4 CLR A ; Clear A F0 MOVX @DPTR, A ; Clear FDB0 Counter ; Check for pending serial input E5 98 MOV A, S0CON 20 E0 04 JB ACC.0, +4 ; Got input, step over return ; No input, set Mode1 + REN0 and return 75 98 50 MOV S0CON, #0x50 ; Bits SM1 and REN0 22 RET ; Get S0BUF and send "R" to ack input E5 99 MOV A, S0BUF ; MOV received byte to ACC FB MOV R3, A ; Store received byte in R3 53 98 EE ANL S0CON, #0xEE ; Clear RI0 and REN0 75 99 52 MOV S0BUF, #0x52 ; Send R 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "1": Map switch, set 1 BB 31 12 CJNE R3, #0x31, +18 ; Compare to "1" D2 F6 SETB B.6 ; Set mapbit 1 C2 F7 CLR B.7 ; Clear mapbit 2 E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send ! to ack 75 99 21 MOV S0BUF, #0x21 ; Send "!" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "2": Map switch, set 2 BB 32 12 CJNE R3, #0x32, +18 ; Compare to "2" C2 F6 CLR B.6 ; Clear mapbit 1 D2 F7 SETB B.7 ; Set mapbit 2 E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send @ to ack 75 99 40 MOV S0BUF, #0x40 ; Send "@" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "3": Map switch, set 3 BB 33 12 CJNE R3, #0x33, +18 ; Compare to "3" D2 F6 SETB B.6 ; Set mapbit 1 D2 F7 SETB B.7 ; Set mapbit 2 E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send # to ack 75 99 23 MOV S0BUF, #0x23 ; Send "#" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "l" to enable logging BB 6C 12 CJNE R3, #0x6C, +18 ; Compare to "l" D2 F0 SETB B.0 ; Set bit 1, log enable C2 F2 CLR B.2 ; Disable streaming logging, in case that was previously set E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send l to ack 75 99 6C MOV S0BUF, #0x6C ; Send "l" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "d" to disable logging BB 64 12 CJNE R3, #0x64, +18 ; Compare to "d" C2 F0 CLR B.0 ; Clear logging flagbit C2 F2 CLR B.2 ; Disable streaming logging, in case that was previously set E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send d to ack 75 99 64 MOV S0BUF, #0x64 ; Send "d" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for "x", do XRAM dump BB 78 21 CJNE R3, #0x78, +33 ; Compare to "x" 75 F0 20 MOV B, #20 ; Set bit 5 only E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte 90 FD AF MOV DPTR, #0xFDAF ; Update DPL in XRAM 74 FF MOV A, #FF F0 MOVX @DPTR, A 90 FD B0 MOV DPTR, #0xFDB0 ; Update DPH in XRAM 74 F7 MOV A, #F7 F0 MOVX @DPTR, A ; Send X to ack and bail with REN0 off - Next time into this loop, we'll start dumping 75 99 58 MOV S0BUF, #0x78 ; Send "x" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI 75 98 40 MOV S0CON, #0x40 ; Serial Mode1, REN0 Disabled (we'll turn it back on when we're done dumping) 22 RET ; Just bail, XRAM dump will start next loop ; Check for incoming "s", XRAM streaming mode BB 73 17 CJNE R3, #0x73, +23 ; Compare to "s" D2 F2 SETB B.2 ; Set bit 1, log enable C2 F0 CLR B.0 ; Disable normal logging, in case that was previously set E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte 90 FD B0 MOV DPTR, #0xFDB0 ; DPTR to FDB0, cycle counter for XRAM dumper E4 CLR A ; ACC = 0 F0 MOVX @DPTR, A ; Set counter byte to 0 ; Send R to ack 75 99 53 MOV S0BUF, #0x53 ; Send "S" 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "p" to dump port SFRs BB 70 3F CJNE R3, #0x70, +63 ; Compare to "p" E5 80 MOV A, P0 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 90 MOV A, P1 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 A0 MOV A, P2 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 B0 MOV A, P3 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 E8 MOV A, P4 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 F8 MOV A, P5 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI E5 FA MOV A, P6 F5 99 MOV S0BUF, A ; Send Byte 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Check for incoming "o" to enable pre-start OBD-II BB 6F 1E CJNE R3, #0x6F, +30 ; Compare to "o" 75 F0 08 MOV B, #8 ; bit 3, prestart OBDII - everything else cleared. E5 F0 MOV A, B 90 FD AE MOV DPTR, #0xFDAE ; Logging Flagbyte F0 MOVX @DPTR, A ; Update XRAM flagbyte ; Send "O" 75 99 4F MOV S0BUF, #0x4F ; Send O 30 99 FD JNB S0CON.1, $ ; Wait on S0CON.TI to be set: transmit has completed C2 99 CLR S0CON.1 ; Clear S0CON.TI ; Reapply the settings found in the RESET routine used to initally configure the serial port 75 98 90 MOV S0CON, #0x90 75 BA 03 MOV S0RELH, #3 75 AA CC MOV S0RELL, #0xCC 53 87 7F ANL PCON, #7F 22 RET ; Send current logbyte, bit by bit in ASCII for readablity. ;--BIT7 E4 CLR A ; Clear A register A2 F7 MOV C, B.7 ; Move bit of B into carry 92 E0 MOV A.0, C ; Move carry into ACC.0 24 30 ADD A, #0x30 ; Add 0x30 to A. ASCII "0". If A.0 is set, A would then be 0x31, ASCII "1". FD MOV R5, A ; For serial output ;--BIT6 E4 CLR A A2 F6 MOV C, B.6 92 E0 MOV A.0, C 24 30 ADD A, #0x30 FE MOV R6, A ;--BIT5 E4 CLR A A2 F5 MOV C, B.5 92 E0 MOV A.0, C 24 30 ADD A, #0x30 FF MOV R7, A ;--SEND 12 86 28 LCALL CODE_8628 ; Send R5/R6/R7 ;--BIT4 E4 CLR A A2 F4 MOV C, B.4 92 E0 MOV A.0, C 24 30 ADD A, #0x30 FD MOV R5, A ;--BIT3 E4 CLR A A2 F3 MOV C, B.3 92 E0 MOV A.0, C 24 30 ADD A, #0x30 FE MOV R6, A ;--BIT2 E4 CLR A A2 F2 MOV C, B.2 92 E0 MOV A.0, C 24 30 ADD A, #0x30 FF MOV R7, A 12 86 28 LCALL CODE_8628 ; Send R5/R6/R7 ;--BIT1 E4 CLR A A2 F1 MOV C, B.1 92 E0 MOV A.0, C 24 30 ADD A, #0x30 FD MOV R5, A ;--BIT0 E4 CLR A A2 F0 MOV C, B.0 92 E0 MOV A.0, C 24 30 ADD A, #0x30 FE MOV R6, A 12 86 17 LCALL CODE_8617 ; Send R5/R6 ; End of subroutine 75 98 50 MOV S0CON, #0x50 ; Serial Mode1, REN0 Enabled 22 RET